| 摘要 |
<p>PURPOSE: To improve the reliability of a multi-processor system by warranting the cache coherence. CONSTITUTION: The snoop circuit 50 receives an output of a 1st comparator 54 to judge matching between other request and a snoop controller 56 and receives an output of a 2nd comparator section 55 to judge whether or not a duplicate bus operation is driven with respect to a same address before the end of one bus operation. A prescribed cash coherence signal is outputted onto a system bus in response to an address match signal between the other request and the cache memory and to the judged result, and a 1st control signal for write back, a 2nd control signal for state update, a 3rd control signal to control a data buffer, and a 4th control signal for retrial of a central processing unit are outputted to a local bus to reference or update data of a state tag memory.</p> |
