| 摘要 |
<p>A system memory unit (16) is provided to a computer system (10) comprising memory address and control generation circuitry (22), a number of banks of extended data out dynamic random access memory (EDODRAM) (24), and a number of registers (26a, 26b). The memory address and control generation circuitry (22) is used to generate memory addresses for the EDODRAMs (24), advantageously delivered over two address bus lines (28a, 28b), as well as control signals for the EDODRAMs (24) and the registers (26a, 26b), including advantageously 'shortened' column address strobe (CAS) signals. The registers (26a, 26b) are used to stage the data being streamed out of or into the EDODRAMs (24). As a result of the advantageous manners in which the memory addresses and the CAS signals are provided, the cycle of a memory access is reduced, even if the slower CMOS technology based circuit elements are used.</p> |
