| 摘要 |
In an address generating device wherein addresses are generated by an address computation part in response to data and control signals read out of an instruction memory and are provided to a memory under test, a command control bit for storing a command control signal is provided in the instruction memory and a command register is provided for storing a command read out of a data area of the instruction memory. The output from the address computation part and the output from the command register are input into a first multiplexer, which selects either one of the two inputs in response to a command control signal read out of the command control bit. The output from the first multiplexer is applied to a descrambler, wherein it is translated to a physical address. A second multiplexer is provided for selecting either one of the outputs from the descrambler and the first multiplexer in such an instance. The second multiplexer is controlled by a descramble inhibit signal read out of a descramble inhibit bit in the instruction memory. |
