| 摘要 |
The voltage multiplier circuit has a capacitor (9) which receives a clock signal (CLK) on one terminal, whilst the other terminal is connected firstly to a supply terminal (2) by the bias of a pre-charging transistor (10), and secondly to an output (5) by the bias of an isolation transistor (11). The circuit controls the operation of the two transistors so they are not conducting at the same time, but the voltages that they control are greater than the highest potential present on their source or their drain terminals. <IMAGE> |
