Load signal generating method and circuit for non-volatile memories.

摘要

A circuit (100) for generating data load pulses (L) of variable length as required, and comprising a source (5) for supplying a short load signal (SP), and a delay element (19) for generating longer pulses (STP) as of the short load signal. A static operating mode is provided wherein a load pulse is generated and maintained throughout static operation or as long as critical conditions (standby state, low voltage) persist. An extended pulse is always generated on exiting static operating mode; and the delay element (19) may be disabled by a command (EN) when extended timing is not required. <IMAGE>