| 摘要 |
An arithmetic unit (ALU) subtracts pairs of numbers (G,D) from an accumulation register (A) and two other registers (R1,R2). The subtraction is made using twos complement signed numbers and a sign bit (S) of the result and two carry bits (C1) (C2) are sent to a conditional circuit (COND). The conditional circuit (COND) uses these bits to instruct a first multiplexer (MUX1) to send either the highest or lowest number as required to a second multiplexer (MUX2) which either sends it or not to the accumulator (A) according to instructions (K) from a control unit (UC). <IMAGE>
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