发明名称 |
Dynamic to static logic translator or pulse catcher |
摘要 |
A system and method is provided which includes a set of N and P type transistors connected such that both positive active and negative dynamic logic input pulses may be received. The pulse catcher circuit of the present invention then outputs a static logic level based upon the input pulses. A first input circuit is included that receives the data signal and outputs a level (voltage or absence of a voltage) to an output invertor circuit which is used in conjunction with a feedback circuit as a latch to maintain the output at the desired level. The feedback circuit ensures that the level will be maintained in a stable state (i.e. ground potential for a logical "0" and Vdd for a logical "1"). In this manner the static logic levels output from the circuit will be maintained until another dynamic pulse is received. Additionally, the pulse catcher circuit will always provide a consistent static logic output, even when both of the dynamic logic input signals are in their active states.
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申请公布号 |
US5461331(A) |
申请公布日期 |
1995.10.24 |
申请号 |
US19940282143 |
申请日期 |
1994.07.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SCHORN, ERIC B. |
分类号 |
H03K19/0948;H03K3/356;(IPC1-7):H03K19/017;H03K19/02 |
主分类号 |
H03K19/0948 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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