| 摘要 |
A sigma-delta analog-to-digital converter (ADC) (80) includes first (81) and second (82) integrators, a quantizer (83) connected to an output of the second integrator (82), and a feedback circuit (84) connected to the output of the quantizer (83). In order to avoid the effects of delays through actual circuit elements, the feedback circuit (84) keeps the feedback signal to the first integrator (81) in a high-impedance state until the quantizer (83) resolves the output of the second integrator (82). Thus, the first integrator (81) avoids temporarily summing a possibly incorrect feedback signal. In addition, the feedback circuit (84) also keeps the first integrator (81) from integrating a sum of an input signal and the feedback signal until the feedback signal is driven to its correct state in response to the output of the quantizer (83). To accomplish these results, the feedback circuit (84) includes a compensation circuit (151) for continually determining when the quantizer (83) resolves.
|
