| 摘要 |
a first NMOS transistor for transmitting a supply voltage from a first supply voltage source to a first node in accordance with a logic state of a digital signal applied to the gate thereof; a first PMOS transistor driven reciprocally with the first NMOS transistor, for transmitting the supply voltage from the first supply voltage source to a second node in accordance with a logic state of a digital signal applied to the gate thereof; a second NMOS transistor for transmitting a voltage on the first node to a ground voltage in accordance with a logic state of a signal applied to the gate thereof from the second node; a third NMOS transistor for transmitting a voltage on the second node to the ground voltage in accordance with a logic state of a signal applied to the gate thereof from the first node; a second PMOS transistor connected between a second supply voltage source and a third node, for inputting a constant voltage applied to the gate thereof to maintain a saturation state and for supplying a predetermined size of current signal to the third node; a third PMOS transistor for transmitting the current signal of the third node to a first output terminal in accordance with a logic state of a signal applied to the gate thereof from the first node; and a fourth PMOS transistor driven reciprocally with the third PMOS transistor, for transmitting the current signal from the third node to a second output terminal in accordance with a logic signal applied to the gate thereof from the second node.
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