| 摘要 |
A circuit, which can be integrated on chips, with a so-called phase-locked loop (FLL circuit) for generation and tuning of an internal clock pulse signal (CLK-IR) in an electronic slave unit (3) connected to a superordinate electronic master unit (1) where the circuit (FLL) during communication between the slave unit (3) and the master unit (1) receives external frequency-stable but noisy clock pulses (EX-CLK) in the form of message packets, a second clock pulse signal internally generated in the FLL circuit, a sampling signal (CLK-SMP), being compared with respect to phase with the external clock pulses (EX-CLK) in a phase-locked loop, whereupon, in dependence on the phase position of the sampling signal (CLK-SMP) compared with the external clock pulses (EX-CLK), control pulses are formed which influence the clock pulse generator for the sampling signal (CLK-SMP), such that this is locked in phase in a definite frequency ratio to the external clock pulse signal (EX-CLK). The internal clock pulse signal (CLK-IR) is compared with respect to frequency with the sampling signal (CLK-SMP), whereupon the internal clock pulse generator (IRC) of the FLL circuit changes frequency in discrete small steps in the internal clock pulse signal (CLK-IR) without any disturbing phase shift until the frequency of the internal clock pulse signal (CLK-IR) of the circuit and the frequency of the external clock pulse signal (EX-CLK) are in agreement. |
