| 摘要 |
PURPOSE:To attain quick processing by configuring the device such that signal processing implemented by a signal processing section is not applied to a 1st value but to only a 2nd value so as to omit undesired address generation. CONSTITUTION:A write address ADR is given to a quantization table 4 and an inverse zigzag conversion section 203a, an effective coefficient NZ is given to an inverse quantization section 202, in which data are inversely quantized by using a quantization table 4. The multiplication in the inverse quantization section 202 is limited to the multiplication between the effective coefficient NZ and a quantization coefficient Qi corresponding to the coefficient NZ, and data including a fixed value '0' and the effective coefficient NZ are not arranged in zigzag conversion but all fixed values '0' are arranged by a number corresponding to a Huffman code block and the effective coefficient NZ is overwritten to a corresponding part. Then an address generating section 207 generates only write addressed ADR corresponding to the effective coefficient NZ and does not generate write addresses ADR corresponding to ineffective coefficient whose value is zero. |
