| 摘要 |
PURPOSE: To provide a multiplying circuit which can operate at a high speed while the circuit is maintained at a small size. CONSTITUTION: A repetitive multiplier having a multiplier core 36 which generates partial results at every repetition. When a multiplication instruction is terminated in an early stage, at least one partial result is sent to a general purpose barrel shift 26 26 for bit rearrangement which varies depending upon the number of repetitions performed before the early termination occurs. The bit-rearranged partial result is then sent to a logic unit 28 and the unit 28 obtains the final result by adding such partial results. |
