| 摘要 |
<p>PURPOSE:To provide a video signal processor capable of simplifying a control software in picture magnification/reduction processings for which the scale of a hardware is reduced. CONSTITUTION:The filter coefficient generation circuit 612 of a first signal processing circuit 61 is linked with the operating mode of a second signal processing circuit, generates the positive filter coefficient of a value corresponding to a magnification ratio at the time of a magnification processing mode and generates the negative filter coefficient of the value corresponding to a reduction ratio at the time of a reduction processing mode. A multiplier 613 multiplies high-band signals in input video signals taken out by a high-pass filter 611 with the filter coefficient supplied from the filter coefficient generation circuit 612. An adder 614 adds the input video signals and multiplied output by the multiplier 613 and outputs filtering-processed video signals to the second signal processing circuit. The second signal processing circuit performs the magnification/reduction processings to the input video signals supplied through the first signal processing circuit.</p> |
