发明名称 DECODER CIRCUIT WITH ENABLE SIGNAL
摘要 <p>PURPOSE:To reduce the number of transistors(TRs) required for configuring the decoder circuit operated by an enable signal and converting n-bit input data into an output signal with a binary digit represented by the input data. CONSTITUTION:The decoder circuit 10 receiving an enable signal is configured by connecting plural stages of partial decoder circuits 11, 12 receiving part of input data D0-Dn-1 and an operating command, different input data are given to partial decoder circuits belonging to other stages, an enable signal EN is given to the partial decoder circuit 11 of a 1st stage as an operation command and an output of each pre-stage is given to each partial decoder of a post-stage as an operation command and outputs of a partial decoder circuit 12 of the final stage are extracted as output signals Y0-YN-1.</p>
申请公布号 JPH07273655(A) 申请公布日期 1995.10.20
申请号 JP19940061832 申请日期 1994.03.31
申请人 FUJI ELECTRIC CO LTD 发明人 MIZOE KIMIYOSHI
分类号 H03M7/00;H03K5/13;(IPC1-7):H03M7/00 主分类号 H03M7/00
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