发明名称 MICROCOMPUTER CIRCUIT
摘要 <p>PURPOSE:To minimize a rise in cost and an increase in the number of components by canceling an apparent operation signal by an output inhibiting circuit and supplying it to a selecting circuit even if the apparent operation signal is supplied to the input terminal of a digital filter connected to a 2nd stand-by switch input terminal when a microcomputer in a wake-up state enters a sleep state. CONSTITUTION:An enable decision circuit 20 is provided. The enable decision circuit 20 consists of four NAND gates 20a, 20b, 20c, and 20d; and the input terminals of the NAND gate 20c is connected to the output terminal of the digital filter 5 connected to three 1st auxiliary switch input terminals 2a and 2b, and the input terminal of the NAND gate 20d is connected to the output terminal of the digital filter 5 connected to 2nd auxiliary switch input terminals 3a and 3b. The NAND gates 20a and 20b among those four NAND gates are supplied with the control signal from a register 10.</p>
申请公布号 JPH07271753(A) 申请公布日期 1995.10.20
申请号 JP19940061475 申请日期 1994.03.30
申请人 KANSEI CORP 发明人 NAGASE HITOSHI
分类号 G06F15/78;(IPC1-7):G06F15/78 主分类号 G06F15/78
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