FLIP-FLOP CIRCUIT

摘要

PURPOSE:To attain a high speed operation by decreasing a current of a data latch differential logic circuit than a current of a data read differential logic circuit so as to reduce a logical level. CONSTITUTION:Master and slave read differential pairs (comprising transistors(TRs) X1 and X2, X3 and X4) form respectively differential pairs with TRs X5, X6 in cascade connection and a TR X7 uses a current path in common. On the other hand, latch differential pairs use differential pairs with TRs XL5, XL6 in cascade connection and the TR X7 uses a current path in common. The size of TRs XLn (n=1-11) being components of the latch differential pairs is selected smaller than the size of TRs Xn (n=1-7) being components of the read differential pairs such that for example, the operating current of the latch differential pairs is reduced to nearly a half of the operating current of the read differential amplifier pairs.