| 摘要 |
PURPOSE: To enhance integration while ensuring a design margin for an adjacent layer by forming two impurity regions and an intermediate channel region on a pillar formed in a shallow trench in a semiconductor substrate and then forming a gate insulation layer and a bit line for the word line of a gate electrode. CONSTITUTION: A word line and a bit line extend, respectively, in the WL and BL directions and a first pillar 18 which is isolated by a first trench is formed along with a second pillar 18a isolated by a second trench. The word line 31 is formed to surround the first pillar 18, while the bit line 27 is formed to surround the second pillar 18a. A channel region 45 is formed between first and second impurity regions 44, 43 formed vertically to the pillars 18, 18a, wherein the first and second impurity regions 44, 43 function, respectively, as drain and source regions. The drain region 44 is connected with the bit line 27, and a storage node 41 is formed on an isolation insulator while surrounding the first pillar 18. |
