| 摘要 |
<p>A self-contained fully programmable digital signal processor (100) has two processors (101, 102) sharing, in parallel interleave fashion, a math unit (103) such as a multiply-and-accumulate circuit. A background processor (102) controls an external dram and preprocesses the information for a foreground processor (101). On-chip sram (107, 110) stores program parameters for both the foreground and background processors and facilitate information transfer between the foreground and background processors. The sram is time-multiplexed to permit access by the foreground processor, the background processor, and external devices without the expense of multiport sram. Flip-flops maintain data signals to the math unit while the sram is being accessed. The foreground processor has a custom instruction set that optimizes the implementation of complex music synthesis filter structures. An on-chip white noise generator quickly provides pseudorandom data for some of the instructions.</p> |
