摘要 |
<p>In a line computer used for controlling a manufacturing line control system, in which a high speed CPU and low speed I/O devices are used, optimum bus timing for signal transmission can be generated, which has enough time margin to adjust speed difference between the high speed CPU and the low speed I/O devices. Further, function of a calendar clock is improved so that the accurate time can be generated. Furthermore, display memory in a CRT displaying controller is used effectively so that the number of memory elements can be reduced. Still furthermore, connection system between the CPU board and I/O boards or floppy disk drives is improved so that abnormality of the peripheral equipments does not expand to the CPU board. Still furthermore, in this invention, compiler type language such as C language can coexist with interpreter type language such as BASIC language.</p> |
申请人 |
YOKOGAWA ELECTRIC CORP., MUSASHINO, TOKIO/TOKYO, JP |
发明人 |
TAIRAKU, HIROKAZU, HACHIOJI-SHI, TOKYO, JP;INOUE, KENICHI, TAMA-SHI, TOKYO, JP;ITO, CHIAKI, FUCHU-SHI, TOKYO, JP;TAKIMOTO, KENJI, FUCHU-SHI, TOKYO, JP;TANIDO, SHIGETOSHI, TOKYO, JP |