Halbleiterspeichergerät.

摘要

An improved semiconductor memory device having a memory array, a dummy celland a redundancy cell column (RLC) is disclosed. At least one dummy capacity cell is connected to the reference bit line (DBL) to which the cell is connected, and also to a redundancy bit line (RBL) to which redundancy cells (RMC) are connected. Therefore, since a capacity on the reference bit line (DBL) is roughly equalized to that on the redundancy bit line (RBL) by these dummy capacity cells, it is possible to prevent erroneous potential level determination by a sense amplifier (SA) for comparing both the potentials on both the bit lines, without being subjected to the influence of supply voltage fluctuations.