Image bus system for processor network

摘要

The image bus system has a parallel peripheral bus (2) of limited length, coupled to the central processor (1) and a compatible image bus (6) coupled to the peripheral devices (7). The peripheral bus and the image bus are couple to respective conversion devices (3,5) coupled together via a transmission medium (4), of long length in comparison to the peripheral bus, for allowing peripheral access to the central processor and transfer of the accessed information. Pref. the conversion devices respond to incorrect information transfer via the transmission medium to provide a fault indication, if initiate an error correction.