Leading zero/one anticipator.

摘要

An apparatus and method for anticipating leading zeros/ones used in normalizing the results of a full adder. The propagate (P), generate (G) and zero (Z) states of the two inputs to the adder are combined in two stages of logic to derive a pair of state outputs L phi S and L1S which fully specify by respective bit strings the leading zero and leading one conditions of the output from the adder. The two state bit strings, one representing the leading zero evaluation and the second representing the leading one evaluation, are then compared to determine which one of the two is applicable, correspondingly indicating whether the adder result is a positive or a negative value, and the number of leading bit positions requiring shifted removal during the normalization process. The leading 0/1 anticipator according to the present invention lends itself to high speed and low device count circuit implementations. <IMAGE>