| 摘要 |
The circuit includes master and slave boards. The master board comprises: a bus use demand arbitration unit for receiving a transmission demand depending upon an interrupt generating signal from a plurality of slave processors through a multi-function chip, and selecting a specific slave processor by the arbitration of the multifunction chip, the bus use demand arbitration unit being controlled by the central processing unit; a bus control and DSACK generating unit for controlling an open/close operation of a data or address buffer during access of a DPRAM, transmitting a chip selecting signal to a slave board, sending the chip selecting signal to the bus use demand arbitration unit, and producing a data transfer and size acknowledge signal in a predetermined time in order to adjust the cycle and the synchronization of the CPU, the bus control and DSACK generating unit being controlled by the CPU; and a master board buffer unit for receiving the signal of the DSACK generating unit, and controlling addresses, data, and buffering of the control signal. The slave board comprises a DPRAM peripheral circuit for separating address, data and control signal lines in the direction of the master of the DPRAM from those of the direction of the slave thereof in order to avoid collision therebetween, the DPRAM peripheral circuit being controlled by the CPU; a bus control circuit for controlling the bus of the DPRAM peripheral circuit, the bus control circuit being controlled by the CPU; and a maser state watching circuit for watching the interrupt of the master board before the slave demands the transmission, and if the master is transmitting the data to the slave, preventing the slave from being a new transmission.
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