Process and device for the implementation of the Viterbi algorithm using a metric memory with reduced bandwidth (longer cycle access time).

摘要

This device comprising a digital signal processor (1) proper, a ROM program memory (2) and a RAM data memory (3) which are connected respectively to the processor, is characterized in that associated with the RAM data memory is a RAM Viterbi memory (7) including means for executing addition, comparison and selection operations of the Viterbi algorithm, and logic (8) for controlling the RAM Viterbi memory (7). The add/compare/select (ACS) procedure computes sixteen new metrics "Ms" from the previous metric "Me" for each sample P(s). Two metrics Ms(j) and Ms(j+8) are computed in parallel. In general, two separate memories Me(2j) and Me(2j+1) are used to improve the bandwidth of the memory and to reduce the number of execution cycles for the ACS algorithm, which only needs one memory cycle.