| 摘要 |
first and second processors constituting a multiprocessor system; first and second cache controllers for executing a cache access control for the first and second processors; a system control multiplexor for receiving a cache control write back signal to latch a write back address of the processors and for supplying the latched address to a comparator; the comparator for comparing the latched address with cache access addresses from the processors to output a compared result; a first arbitrating unit for receiving the compared result to arbitrate whether the cache access in the first processor is executed; a first transmission error detecting logic for receiving an uplive signal from the first arbitrating unit to execute the access of the first processor or for receiving the compared result to stop the access of the first processor; a second arbitrating unit for receiving the compared result to arbitrate whether the cache access in the second processor is executed; a second transmission error detecting logic for receiving an uplive signal from the second arbitrating unit to execute the access of the second processor or for receiving the compared result to stop the access of the second processor.
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