Instruction pipeline sequencer in which state information of an instruction travels through pipe stages until the instruction execution is completed

摘要

A microprocessor comprised of Instruction Fetch Unit (10), Instruction Decoder (12), Pipeline Sequencer (14), Register File (16), Multiply/Divider-Unit, Execution Unit, and REG coprocessors block (18) and instruction cache, Address Generation Unit, local register cache, and MEM coprocessors block (20). The Instruction Cache provides the Instruction fetch unit (10) with instructions every cycle. The instruction sequencer (IS) includes the Fetch Unit (IFU-10), the Instruction Decoder (ID-12) and the Pipeline Sequencer (PS-14). The instruction sequencer can decode and issue up to three instructions per clock. The pipe sequencer (14) employs a write back path to store snap shots of the state of the machine in pipe stages 1 and 2. This provides the way for branch guessing and the process switching to correct itself after issuing a wrong IP (in the case of the branch guessing), or a way to preserve the internal state of the machine at the time a context switching occurs in order to come back to the same condition it had left.