Very large scale integrated planar read only memory

摘要

In a read-only memory core improved generation of a trigger signal, TRIG, is achieved through the use of a pair of cascaded CMOS differential amplifiers which are directly interconnected and directly coupled to a CMOS inverter from which the trigger signal, TRIG, is derived. The cascaded differential amplifiers have trigger points set by varying the channel widths of the input FETs to the CMOS differential amplifiers, or by adjusting the gains of the CMOS differential amplifiers to match the trigger point of the CMOS inverter coupled to its output. The trigger circuit is powered down to zero power dissipation whenever it is inactive.