| 摘要 |
A test access port (TAP) controls monitoring and testing of static current IDDQ in integrated circuit (IC) devices having both a TAP of the type specified in IEEE Standard 1149.1 Test Access Port and Boundary Architecture and built-in current (BIC) monitors. BIC monitors are coupled between MOS or CMOS modules of the IC device and the low potential power rail (GND) for monitoring static current IDDQ. Bypass or shunt MOS transistors (N1,N2, . . . , NN) are coupled with primary current paths in parallel with the respective BIC monitors between the CMOS circuit modules and low potential power rail (GND). The TAP data registers (TDR's) include a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin. BICSC TDR outputs are coupled to control nodes of the respective MOS bypass transistors (N1,N2, . . . , NN) for controlling the conducting state of the bypass transistors according to the BICBC. The MOS bypass transistor provides a low impedance bypass path around the BIC current monitor in response to a first BICBC during normal operation of the IC device and presents a high impedance bypass path in response to a second BICBC for monitoring quiescent IDDQ at the BIC monitor.
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