| 摘要 |
PURPOSE:To make high integration of memory element easier with simple structure by laminating a ferroelectric layer an a semiconductor layer, sandwiching the layer with a pair of electrodes for a diode element, and letting excessive current to flow by applying the voltage higher than operating voltage between electrodes at specific temperature. CONSTITUTION:A ferroelectric layer 1 is laminated an a semiconductor substrate 2, and sandwiched between a pair of electrodes 4 and 5 for a diode element. Then, excessive current, normally 10<-5>-10<-3>A/cm<2>, is let to flaw by applying higher voltage than operating voltage, at 0 deg.C or more, between both electrodes 4 and 5. When operating voltage lower than that voltage, typically 1/100-1/2 of it, is applied immediately after the current is permitted to flaw and the current value is measured, the value is larger than in no process. The low resistance state is kept about one minute. Since this time is long enough as compared with the refresh time of DRAM, so memory configuration of DRAM type is possible. |
