| 摘要 |
<p>PURPOSE:To match phases of write frequency division clocks used to write input data in a memory circuit in the speed converter of redundant configuration. CONSTITUTION:Input data S14 are written in a memory circuit 102A synchronously with a write frequency division clock S11A and output data S16A are read from the circuit 102A synchronously with a read frequency division clock S13A. A write clock frequency divider 101A frequency-divides a 1st clock S10 to produce a clock S11A and a read clock frequency divider 103A frequency- divides a 2nd clock S 12 to produce a clock S13A. A phase comparator 104A produces a stuff request signal S15A based on the result of phase comparison between the clocks S11A and S13A. Upon the receipt of a switching signal S12 to select a speed conversion circuit 1B, the frequency divider 101A makes the phase of the clock S11A matchs with a phase of a frequency division timing pulse S22B from the 2nd speed conversion circuit 1B.</p> |
