| 摘要 |
PURPOSE:To reduce the size of the circuit and to adapt the circuit for circuit integration processing by reducing the circuit scale of the pi/4 shift QPSK syn chronization circuit. CONSTITUTION:An IF signal is given to a distributer 1, in which the signal is distributed into two, each is modulated with an orthogonal local signal obtained from an output of a VCO 2 at a 90 deg. distributer 3 by balanced modulators 4-1, 4-2 and I, Q signals are obtained through LPFs 5-1, 5-2. The I, Q signals are binary-shaped at comparators 6-1, 6-2 and signals (i), (q) are outputted. On the other hand, the quantity of the signal I and that of the signal Q-bar are compared and the quantity of the signal I and that of the signal Q are compared to obtain an output of signals i', q'. An output of an exclusive OR (9-4) between a symbol rate 1/2 clock signal and an exclusive OR (9-3) (between an EX-OR (9-1) of the signals i, q and an EX-OR (9-2) of the signals i', q') is used for a control voltage input to the VCO 2 via a loop filter 10. |
