发明名称 SYNCHRONOUS DRAM
摘要 <p>PURPOSE:To increase the speed of continuous reading of data from different banks and to attain high-speed reading from an arbitrary address in an SDRAM performing the operation in synchronization with a clock supplied from the outside. CONSTITUTION:When data are continuously read from different banks 51-54 and each of the banks 51-54 is selected as the reading object, the number of clocks CLK subtracted by one from the number of banks, i.e., three clocks CLK are made not to be supplied after that. Data D4-D4 from the banks 51-54 are multiply out putted by shifting by one clock of the clocks CLK, the data D1-D4 outputted multiplexed, by are selected by means of an output data selecting circuit 7 and outputted to the outside.</p>
申请公布号 JPH07262767(A) 申请公布日期 1995.10.13
申请号 JP19940047030 申请日期 1994.03.17
申请人 FUJITSU LTD 发明人 YANAGISAWA MAKOTO;MOCHIZUKI HIROHIKO;OKA TOMOHARU;KODAMA YUKINORI;SUZUKI TAKAAKI;TAKEMAE YOSHIHIRO;TAGUCHI MASAO;HATAKEYAMA ATSUSHI;OGAWA JUNJI
分类号 G11C11/401;G06F1/06;G06F12/00;G06F12/06;G11C11/407;G11C11/409;(IPC1-7):G11C11/401 主分类号 G11C11/401
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