| 摘要 |
An accumulating multiplication circuit comprises a multiplication part receiving first and second input data, each composed of "n" bits, so as to output a first 2n-bit data of a partial product of the first and second input data, and a shifter for shifting the "2n-bit" data, which is the subject of the arithmetical operation, rightward by "n" bits. An arithmetical operation part receives the first 2n-bit data and the right-shifted 2n-bit data so as to output a third 2n-bit data. Thus, a double-precision multiplication can be efficiently executed.
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