| 摘要 |
The apparatus comprises an input test pad having an input terminal A and a test input terminal in common; a P-type transistor for controlling a charge level of a first node according to a signal level inputted from the input test pad; a transistor for controlling a charging level of a second node according to the charge level of the node controlled by the P-typed transistor; transmission gates for controlling electric charge of each node according the signal level inputted from the input test pad; a first inverter with transistors for inverting the state of the second node, for then applying it to a second inverter and a NAND gate, and controlling an output of the NAND gate; and the second inverter for inverting an output of the first inverter, applying it to an input terminal of the NAND gate, and controlling the output of the NAND gate.
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