| 摘要 |
<p>In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units (60, 61) for integrity, which BPUs (60, 61) are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit (70) for receiving data manipulation results from both BPUs (60, 61) and for transferring specified information words simultaneously to both BPUs (60, 61) upon request. In each BPU (60, 61), parity is generated for control groups, which are made up of cache interface control signals generated by each BPU (60, 61). Parity for the groups sent to the cache unit (70) and the other respective BPU (60, 61) are checked for errors in both the cache unit (70) and the respective BPU (60, 61), and in the event that an error is sensed, an error signal is issued to institute appropriate remedial action.</p> |
