| 摘要 |
<p>An improved circuit for compensating an input/output characteristic linearity of a parallel comparison type analog-to-digital converter which reduces a wasteful consumption of current in the linearity compensation circuit. In the improved linearity compensation circuit(5), a dummy circuit (6a) having the same construction as a bias circuit (6) of each comparator of the A/D converter is installed for providing a current IE which is an amplification of an input current by means of the input circuit of each comparator(COP), a first current multiplier is installed for providing a multiplied current kIE on the basis of the current provided by the dummy circuit (6a), an amplifier is installed for providing a current ki which corresponds to a multiplication of the current i by an amplification factor of the input circuit, and a second current multiplifier is installed for providing another multiplified current k l i which is a multiplication of the current ki by l . The other multiplied current k l is auxiliarily supplied to the input circuit. Therefore, the wastefully consumed current can be reduced to approximately kIE.</p> |
