发明名称 |
Redundancy circuitry layout for a semiconductor memory device. |
摘要 |
<p>A Redundancy circuitry layout for a semiconductor memory device comprises an array (MAR) of programmable non-volatile memory elements (TF0,TF1) for storing the addresses of defective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines; the redundancy circuitry layout is divided in identical layout strips (LS1-LS4) which are perpendicular to the array (MAR) of memory elements (TF0,TF1) and which comprise each a first and a second strip sides located at opposite sides of the array (MAR) of memory elements (TF0,TF1), the first strip side containing at least one programmable non-volatile memory register (CRRA,CRRB) of a first plurality for the selection of redundancy bit lines and being crossed by a column address signal bus (CABUS) running parallel to the array (MAR of memory elements (TF0,TF1), the second strip side containing one programmable non-volatile memory register (RRR) of a second plurality for the selection of redundancy word lines and being crossed by a row address signal bus (RABUS) running parallel to the array (MAR) of memory elements (TF0,TF1). <IMAGE></p> |
申请公布号 |
EP0675440(A1) |
申请公布日期 |
1995.10.04 |
申请号 |
EP19940830146 |
申请日期 |
1994.03.29 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.R.L. |
发明人 |
PASCUCCI, LUIGI;CARRERA, MARCELLO;DEFENDI, MARCO |
分类号 |
G11C17/00;G11C5/02;G11C16/06;G11C29/00;G11C29/04;H01L21/82;H01L21/822;H01L27/04;H01L27/10;(IPC1-7):G06F11/20 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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