发明名称 Data processing device for maintaining coherency of data stored in main memory, external cache memory and internal cache memory
摘要 A fetching operation break unit breaks a fetching operation of a block data from a main memory, when a system bus is released during the fetching of the block data and also when data written due to a write access by an external device into the main memory coincides with the fetching of one block data. Further, a notification means notifies the state of the fetching operation to an external cache memory. Therefore, the external cache memory can confirm whether a block-in operation of the microprocessor is broken or not, and the contents of the external cache can correctly coincide with the contents of the internal cache and the main memory by carrying out a steal operation, so that the operational reliability of a computer system can be increased.
申请公布号 US5455925(A) 申请公布日期 1995.10.03
申请号 US19930111731 申请日期 1993.08.23
申请人 FUJITSU LIMITED 发明人 KITAHARA, TAKESHI;MITSUHASHI, MASATO;FUJIHIRA, ATSUSHI
分类号 G06F12/08;(IPC1-7):G06F12/06;G06F13/00 主分类号 G06F12/08
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