| 摘要 |
<p>PURPOSE:To obtain optimum performance at all times even against a change in a state of a chip by measuring a delay in an in-chip circuit and controlling a clock frequency based on the result of delay measurement. CONSTITUTION:An inverter chain 3 acts like a delay circuit providing a longer delay than a half of a delay time of a critical path and consists of plural stages of inverters, receives a clock signal from an oscillator 1 and provides an output of a delayed input signal. A DFF 5 is employed for a comparator circuit, which receives a clock signal from the oscillator 1 at its clock input and receives an output of the inverter chain 2 at its D input to make comparison. When the delay time of the inverter chain 3 is shorter than the delay time by the critical path, the comparator circuit compares the rising of the clock signal from the oscillator 1 with the trailing of the delayed clock signal from the oscillator 1. When the delay time of the inverter chain 3 is longer than the delay time by the critical path, the comparator circuit compares the rising of a nearly one preceding clock signal from the oscillator 1 derived from the inverter chain 3 with the trailing of the delayed clock signal from the oscillator 1.</p> |
