发明名称 |
Programmable clock tuning system and method |
摘要 |
A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.
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申请公布号 |
US5455931(A) |
申请公布日期 |
1995.10.03 |
申请号 |
US19930155178 |
申请日期 |
1993.11.19 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CAMPORESE, PETER J.;MEANEY, PATRICK J.;O'LEARY, BRIAN J.;RIZZOLO, RICHARD F. |
分类号 |
G06F1/10;G06F17/50;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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