| 摘要 |
PURPOSE: To provide a synchronous memory device with which write waiting time can be controlled. CONSTITUTION: As a write waiting time control method for the synchronous memory device with which data processing can be performed synchronously with a system clock CLK to be impressed, a write waiting time signalϕWL1 enabling the arbitrary change of logic value is generated 10. Corresponding to this write waiting time signalδfL1, logical state hold time based on the system clock CLK is set to a column address counter 30 for generating a column address signal CAi, burst length counter 50 for counting the burst length of data, and data transmission switch circuit 90 for controlling write data transmission to an internal data bus. A write waiting time control signal generation circuit 10 for generating the write waiting time signalϕWL1 can easily change the output logic value by the disconnection, etc., of wire bonding or fuse.
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