| 摘要 |
A high density ASIC cell provides customization solely at the polysilicon #2, insulator #3 levels. High density is achieved by permitting a metal #1 trace to traverse an underlying transistor, without requiring space between adjacent transistors to facilitate traversing interconnects. Oversized collector and emitter traces at the polysilicon #1 level make downward contact with the collector and base regions of the underlying transistor, and provide redundant upward contact with collector and emitter polysilicon #2 traces. Contact between the transistor base and a base polysilicon #2 trace is also made. The polysilicon #2 emitter, base and collector traces provide a replicated, unvarying pattern that preferably defines a 3x3 matrix of potential contact points for overlying metal #1 traces to contact the underlying transistor's emitter, base and collector. A metal #1 trace can traverse this 3x3 matrix simply by not providing openings in the insulating #3 layer beneath the traverse. If a metal #1 trace is to contact a region of the underlying transistor, an opening is made in the insulation #3 layer over the necessary contact in the 3x3 matrix at the polysilicon #2 level. Thus, customization of the ASIC is made at the metal #1 level, and at the insulation #3 level by determining which metal #1 traces will contact what regions of the underlying transistor.
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