Multi-bit test circuit for solid state memory circuits

摘要

The test circuit includes acquisition units (30) with read amplifiers (30A,30B) connected to respective memory cells. Direct read amplifiers (30C) are also included. Each amplifier receives input from a bit line and a complementary line. The acquisition lines are coupled to the memory cells and the individual amplifiers produce output via a single pair of lines (S,S') when selectively activated. A further amplifier circuit is connected to these output lines to provide the final system output values.