Quantising and dequantising circuit with reduced size.

摘要

A quantising and dequantising circuit (3) has a first memory circuit (31) with integer addresses, in which reciprocal data is stored, and a second memory circuit (32), in which a quantisation table of integers is stored. The integers stored in the second memory circuit (32) are provided to the first memory circuit (31) as address signals, causing output of the corresponding reciprocal data. Data to be quantised is multiplied by the reciprocal data output by the first memory circuit (31). Data to be dequantised is multiplied by the integers output from the second memory circuit (32). <IMAGE>