| 摘要 |
Memory cells (10) are arrange in the row and column directions in the form of a matrix. A transistor (17) as a load is connected to column lines (C1, C2 - Cn). A sense amplifier (32) is connected to the transistor (17). In a read check operation, in which the data in the memory cells (10) are erased, and the erased state of each memory cell is checked, all the row lines are set in a non-selected state by a row decoder (11), and all the column lines are selected by a column decoder (12). In this state, the sum of currents flowing in the memory cells (10) is detected by the sense amplifier (32). When the current detected by the sense amplifier (32) becomes a predetermined value, a data erase operation is ended. <IMAGE> |
