发明名称 |
Five transistor memory cell with shared power line |
摘要 |
Static random access memory cells (SRAMS) containing five MOS transistors are configured in a memory array such that only three bitlines are required for two cells. A first bitline is coupled to a first side of a first memory cell, and a second bitline is coupled to a first side of the second memory cell. The first and second memory cells share either a common power bitline or a common ground bitline. A control circuit executes a special write operation to write a low logic level on the second side of the memory cells. The control circuit is coupled to the first, second, and third bitlines to generate a first differential voltage across the memory cells that is lower than the operating voltage on the third bitline and to generate a second voltage lower than the operating voltage on the second bitline when storing a low logic level on the second side of the first storage cell. To perform a special write operation on the second storage cell, the control circuit generates the first differential voltage on the third bitline and the second voltage on the first bitline.
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申请公布号 |
US5453950(A) |
申请公布日期 |
1995.09.26 |
申请号 |
US19950377952 |
申请日期 |
1995.01.24 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
VOSS, PETER H.;LINDEN, JEFFREY L. |
分类号 |
G11C11/412;H01L21/8244;H01L27/11;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/412 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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