BUS CONTROL LOGIC OVERRIDES MEMORY ARBITRATION CONTROL LOGIC FOR DUAL BUS ARCHITECTURE COMPUTER,申请号NZ19920245344-传众专利搜索

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发明名称	BUS CONTROL LOGIC OVERRIDES MEMORY ARBITRATION CONTROL LOGIC FOR DUAL BUS ARCHITECTURE COMPUTER
摘要
申请公布号	NZ245344(A)	申请公布日期	1995.09.26
申请号	NZ19920245344	申请日期	1992.12.02
申请人	INTERNATIONAL BUSINESS MACHINES CORP	发明人	AMINI, NADER;BOURY, BECHARA FOUAD;BRANNON, SHERWOOD;HORNE, RICHARD LOUIS;LOHMAN, TERRENCE JOSEPH
分类号	G06F13/36;G06F13/16;(IPC1-7):G06F13/16;G06F15/76	主分类号	G06F13/36
代理机构		代理人
主权项
地址

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