发明名称 Cache memory support in an integrated memory system
摘要 A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.
申请公布号 US5454107(A) 申请公布日期 1995.09.26
申请号 US19930159186 申请日期 1993.11.30
申请人 VLSI TECHNOLOGIES 发明人 LEHMAN, JUDSON A.;NAKAHARA, MIKE;RICHARDSON, NICHOLAS J.
分类号 G06F12/08;G09G5/36;G09G5/39;(IPC1-7):G06F15/20;G06F13/00 主分类号 G06F12/08
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