| 摘要 |
PURPOSE:To provide a digital PLL circuit which extracts an average frequency and can supply a clock that includes no low frequency jitter component. CONSTITUTION:This digital PLL circuit consists of a reproduction clock supply means 1 which outputs a reproduction clock of fixed frequency fOSC and switches this reproduction clock to a reproduction clock fL lower than the minimum frequency fMIN of a reference clock fREF or to a reproduction clock fH higher than the maximum frequency fMAX, a phase comparing part 30 which compares the clocks fL and fH with the clock fREF in terms of phases in a reproduction clock cycle and produces a binary detection signal to show both clocks fL and fH have advanced or lagged phases to the clock fREF and outputs this detection signal as a control signal, and a counter 40 which counts the frequency when the detection signal shows the advanced or lagged phase for a prescribed period and outputs the count value as the frequency data corresponding to the clock fREF. |
