| 摘要 |
The device is applied to the processor communication of distributed control system, and reduces the delay time for bus communication. The device includes local higher/lower counters(11,12) which select the link address by round robbin method, a counter-part address register(14) which saves the address of received processor, a self address register(15) which saves the address of transmission processor, a comparator(13) which compares the value between a counter-part address and self address, and a local-counter stop signal generator(16) which reserves the transmission of data. The device further includes 1st AND logical means(18), 2nd AND logical means, 3rd AND logical means, OR logical means(20), and a buffer enable signal generator(17).
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